1. Field
Exemplary embodiments of the present invention relate to a memory and a memory system including the same.
2. Description of the Related Art
A memory cell of a memory includes a transistor serving as a switch and a capacitor for storing electrical charge, i.e. data. According to whether or not the capacitor in the memory cell stores electrical charge, i.e. according to whether a potential between both terminals of the capacitor is high or low, a logic level of data is determined as a high level (logic “1”) or a low level (logic “0”).
Since the data is stored in the capacitor in the form of an accumulated electrical charge, it would be ideal that there is no power consumption of the stored electrical charge. However, since current leakage occurs due to a PN junction of a metal oxide semiconductor (MOS) transistor, the stored initial electrical charge may be discharged, and thus the stored data may be lost. To prevent such data loss, it is necessary to read data stored in a memory cell and to recharge the memory cell based on the read data before the data is lost. Such an operation of recharging the memory cell is called a refresh operation. The refresh operation should be periodically performed to maintain stored data.
FIG. 1 is a diagram illustrating a part of a cell array included in a memory for describing a word line disturbance.
In FIG. 1, “WLK−1” “WLK”, and “WLK+1” indicate three word lines which are disposed one by one in a cell array. The word line WLK indicated by “HIGH_ACT” represents a frequently activated word line, which has a large number of activation times or a high activation frequency, and the word lines WLK−1 and WLK+1 represent adjacent word lines, which are disposed adjacent to the frequently activated WLK. “CELL_K−1”, “CELL_K”, and “CELL_K+1” indicate memory cells coupled to the word lines WLK−1, WLK, and WLK+1, respectively. The memory cells CELL_K−1, CELL_K, and CELL_K+1 include cell transistors TR_K−1, TR_K, and TR_K+1, and cell capacitors CAP_K−1, CAP_K, and CAP_K+1, respectively. For reference, “BL” and “BL+1” indicate a bit line.
When the frequently activated word line WLK is activated or precharged, voltages of the adjacent word lines WLK−1 and WLK+1 increase or decrease due to a coupling phenomenon occurring between the word lines WLK, WLK−1 and WLK+1. Accordingly, the amount of charges stored in the cell capacitors CAP_K−1, CAP_K, and CAP_K+1 is affected. Therefore, when the frequently activated word line WLK is toggled between an active state and a precharge state, data stored in the cell capacitors CAP_K−1 and CAP_K+1 may be lost due to a change in the amount of charge stored in the cell capacitors CAP_K−1 and CAP_K+1.
In addition, an electromagnetic wave is generated while a word line is toggled between an active state and a precharge state, and the electromagnetic wave allows electrons to flow into or flow out of a cell capacitor included in a memory cell which is coupled to adjacent word lines. As a result, data stored in the memory cell may be lost.